The present invention relates to a semiconductor device and a technique for manufacturing the same. Particularly, the present invention is concerned with a semiconductor device having a capacitor of MIM (Metal Insulator Metal) structure and a technique applicable effectively to a manufacturing technique for the semiconductor device.
In an LSI for communication and a high-speed CMOS logic device, it is essential to make the dielectric constant of an interlayer insulating film low and adopt Cu wiring with use of the Damascene method, as a technique for attaining a high-speed circuit operation. The LSI for communication and the CMOS logic device generally include a capacitor of MIM structure within an analog circuit.
The technique for fabricating a capacitor of MIM structure is described, for example, in Japanese Published Unexamined Patent Application No. 2004-146814 (Patent Literature 1), No. 2004-253481 (Patent Literature 2), No. 2004-247520 (Patent Literature 3), and No. 2004-119461 (Patent Literature 4). Among them, Patent Literature 1 discloses a technique for forming a lower electrode of a capacitor by the Damascene method.
[Patent Literatures]                1. Japanese Unexamined Patent Publication No. 2004-146814        2. Japanese Unexamined Patent Publication No. 2004-253481        3. Japanese Unexamined Patent Publication No. 2004-247520        4. Japanese Unexamined Patent Publication No. 2004-119461        